Tong Family

IDF Fall 2005 wrap – The Tech Report – Page 1 [T]he biggest news out of IDF, Intel’s decision to move to a new CPU microarchitecture common to its mobile, desktop, and server product lines, and we’ve outlined some of the features of that architecture, including a 14-stage pipeline that’s much shorter than the 31-stage monster in current Pentium 4 and Pentium D chips. This new CPU core will be a four-issue design, which means it has more internal parallelism than the three-issue designs in most current x86 processors, including the Pentium M, Pentium 4, and Athlon 64. Done correctly, this new core should achieve higher performance per clock and per watt than Intel’s current CPU cores.
_And codenames galore…_ Merom is the code-name for the mobile version of Fred, intended for Socket 479. The desktop part, code-named Conroe, will come in an LGA775 package, and will have two versions that differ in terms of cache size. All of these chips will be dual-core parts manufactured on Intel’s 65nm process. On the server front, Fred will have two incarnations at 65nm: a dual-core chip with 4MB of L2 cache known as Woodcrest, and a quad-core processor with 16MB of L2 cache code-named Whitefield.
These parts ship in early 2006.
Napa is the next generation mobile set of chips branded the Centrino. Yonah, the first dual-core version of the Pentium M, that will be part of the Napa platform due in early 2006. Yonah is essentially a waypoint between the current Pentium M architecture and Intel’s future, common microarchitecture. There’s more to the Napa platform than just Yonah, of course. The core-logic chipset, code-named Calistoga, will be a mobile version of the 945 Express chipset. There’s also an Intel wireless networking solution.